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Freescale Semiconductor Technical Data
MC33797 Rev 2.0, 07/2005
Four Channel Squib Driver IC
The Four Channel Squib Driver IC is a complete squib diagnostic and deployment interface for use in automotive air bag modules. Extensive diagnostics and system control features are incorporated to provide fail-safe operation. The device contains a serial peripheral interface (SPI) compatible 8-bit interface to allow microprocessor control. The device has the capability to be used in a standard four-channel squib driver IC or in a cross-coupled state with the high- and low-side squib drivers located on separate squib driver ICs. Both the high- and low-side output drivers are protected against temporary shorts to battery or ground. The current limit threshold is set by an external resistor. Features * Four-Channel High-Side and Low-Side 2.0 A FET Switches * Externally Adjustable FET Current Limiting * Adjustable Current Limit Range: 0.8 A to 2.0 A * Individual Channel Current Limit Detection with Timing Duration Measurement, Communicated via SPI * 8-Bit SPI for Diagnostics and FET Switch Activation * Diagnostics for High-Side Safing Sensor Status * Resistance and Voltage Diagnostics for Squibs * Squib Driver IC Capability to Be Used for Cross-Coupled Driver Firing Application (Allows High- and Low-Side FET Switches to Be Located on Separate Squib Driver ICs) * Pb-Free Packaging designated by Suffix Code EK
33797
SQUIB DRIVER
EK SUFFIX (Pb-Free) 98ARH99137A 32-TERMINAL SOICW
ORDERING INFORMATION
Device MC33797EK/R2 Temperature Range (TA) -40C to 85C Package 32 SOICW
VPWR
VIN
33797
VBOOST1 TYPICAL AIR BAG POWER SUPPLY VBOOST2 FIRING CAP FIRING CAP VDIAG_1 VFIRE_1A VFIRE_1B VDIAG_2 VFIRE_2A VFIRE_2B VDD CS CLK MISO MOSI RST FEN_1 FEN_2 R_LIMIT_1 R_LIMIT_2 SENSE SQB_LO VFIRE_RTN SQB_HI
/4 SQUIB (1A, 1B, 2A, 2B)
/4 /4 /2
5.0 V
R_DIAG
MICROPROCESSOR
ENABLE ENABLE
GND
Figure 1. 33797 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VFIRE_2B
VDIAG_2
FEN_1
FEN_2
VDIAG_1
VFIRE_1B VFIRE_1A SQB_HI_1A SENSE_1A SQB_LO_1A VFIRE_RTN SQB_LO_1B SENSE_1B SQB_HI_1B R_LIMIT_1 R_LIMIT_2 Analog Integrated Circuit Device Data Freescale Semiconductor
MOSI
MISO
SQB_HI_2A SENSE_2A
Driver Control
SQB_LO_2A VFIRE_RTN
SQB_LO_2B
Driver Control
Control and Diagnostic Multiplex
SENSE_2B
SQB_HI_2B
RST R_DIAG
GND
Figure 2. 33797 Simplified Internal Block Diagram
33797
2
Driver Control
Driver Control
VFIRE_2A
VDD
CLK
CS
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
SQB_LO_1A SENSE_1A MOSI CLK SQB_HI_1A VFIRE_1A VDIAG_1 GND MISO VDD VFIRE_1B SQB_HI_1B FEN_1 R_LIMIT_1 SENSE_1B SQB_LO_1B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SQB_LO_2A SENSE_2A CS RST SQB_HI_2A VFIRE_2A VDIAG_2 VFIRE_RTN VFIRE_RTN R_DIAG VFIRE_2B SQB_HI_2B FEN_2 R_LIMIT_2 SENSE_2B SQB_LO_2B
Figure 3. Terminal Function Description
Table 1. Terminal Function Description
Terminal 1 2 Terminal Name SQB_LO_1A SENSE_1A Terminal Function Output Input Formal Name Squib Lo 1A Squib Sense 1A Terminal Description Drain of the low-side switch that connects to the low terminal of Squib_1A Used during standard applications involving a four-channel squib driver IC or during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). Serial data input for SPI interface. Serial clock input for SPI interface. Drain of the high-side switch that connects to the low terminal of Squib_1A Firing supply terminal for Squib_1A. Diagnostic terminal for high-side safing sensor for squibs 1A and 1B and the VFIRE supply voltage. Device ground terminal for internal logic and diagnostic circuitry. Serial data output for SPI interface. Device power terminal for internal logic and diagnostic circuitry. Firing supply terminal for Squib_1B. Drain of the high-side switch that connects to the low terminal of Squib_1B Active high input signal to enable operation of the squib_1A and Squib_1BFET drivers. External resistor to ground is used to set current limit for Squib_1A and squib_1B FET drivers.
3 4 5 6 7 8 9 10 11 12 13 14
MOSI CLK SQB_HI_1A VFIRE_1A VDIAG_1 GND MISO VDD VFIRE_1B SQB_HI_1B FEN_1 R_LIMIT_1
Input Input Output Supply Input Ground Output Input Supply Output Input Output
Data Input 1 Serial Clock Squib Hi 1A Squib Firing Supply 1A Squib Diagnostic 1A and 1A Device Ground Data Output 0 Logic Power Squib Firing Supply 1B Squib Hi 1B FET Driver 1A and 1B Limit Resistor - 1A and 1B
33797
Analog Integrated Circuit Device Data Freescale Semiconductor
3
TERMINAL CONNECTIONS
Table 1. Terminal Function Description (continued)
Terminal 15 Terminal Name SENSE_1B Terminal Function Input Formal Name Squib Sense 1B Terminal Description Used during standard applications involving a four-channel squib driver IC and during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). Drain of the low-side switch that connects to the low terminal of Squib_1B Drain of the low-side switch that connects to the low terminal of Squib_2B Used during standard applications involving a four-channel squib driver IC and during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). External resistor to ground is used to set current limit for Squib_2A and squib_2B FET drivers. Active high input signal to enable operation of the squib_2A and Squib_2B FET drivers. Drain of the high-side switch that connects to the low terminal of Squib_2B. Firing supply terminal for squib_2B. External resistor to ground is used to set the diagnostic current for squib resistance. Power Ground for squibs 1A, 1B, 2A, and 2B Power Ground for squibs 1A, 1B, 2A, and 2B Diagnostic terminal for high-side safing sensor for squibs 2A and 2B and the VFIRE supply voltage. Firing supply terminal for squib_ 2A Drain of the high-side switch that connects to the low terminal of Squib_2A Reset, Active Low Chip Select for SPI interface, Active Low Used during standard applications involving a four-channel squib driver IC or during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). Drain of the low-side switch that connects to the low terminal of Squib_2A
16 17 18
SQB_LO_1B SQB_LO_2B SENSE_2B
Output Output Input
Squib Lo 1B Squib Lo 2B Squib Sense 2B
19 20 21 22 23 24 25 26 27 28 29 30 31
R_LIMIT_2 FEN_2 SQB_HI_2B VFIRE_2B R_DIAG VFIRE_RTN VFIRE_RTN VDIAG_2 VFIRE_2A SQB_HI_2A RST CS SENSE_2A
Output Input Output Supply Input Ground Ground Supply Supply Output Input Input Input
Limit Resistor - 2A and 2B FET Driver 2A and 2B Squib Hi 2B Squib Firing Supply 2B Limit Resistor Diagnostic Squib Fire Power Ground Squib Fire Power Ground Squib Diagnostic 2A and 2b Squib Firing Supply 2A Squib Hi 2A Reset Chip Select Squib Sense 2A
32
SQB_LO_2A
Output
Squib Lo 2A
33797
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Analog Integrated Circuit Device Data Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings (1) All voltages are with respect to ground unless otherwise noted.
Rating INPUT ELECTRICAL RATINGS Voltage on VDD Voltage on Input terminals CS, CLK, D1, D0, FEN_1, FEN_2, RESETB, R_DIAG, R_LIMIT_X Voltage on Squib terminals SQB_HI_XX, SQB_LO_XX, SENSE_XX Voltage on terminals VDIAG_X, VFIRE_XX ESD Voltage Human Body Model Machine Model (3) Maximum VVFIRE with Pulsed Output (4), (5) RSQUIB = 2.0 , tON = 0.8 ms, ISQUIB = 2.24 A RSQUIB = 1.2 , tON = 0.8 ms, ISQUIB = 2.24 A RSQUIB = 0.1 , tON = 0.60 ms, ISQUIB = 2.24 A THERMAL RATINGS Storage Temperature Junction Temperature Ambient Continuous (Prior to Squib Deployment) t 5.0 ms (Post-Squib Deployment) Lead Soldering Temperature (6) Thermal Resistance (Junction-to-Ambient) OPERATING RATINGS (7) Low-Side FET Fire Conditions RSQUIB 2.0 1.2 0.1 tON 2.6 ms 2.6 ms 2.6 ms ISQUIB 3.0 A 3.0 A 3.0 A VSQUIBHI 16 V 16 V 16 V TSTG TA TJCONT TJDPYD TSOLDER RJ-A 155 85 100 300 245 74 C C/W C C
(2)
Symbol
Value
Unit
VDD VI VVFIRE_XX VDIAG_X
7.0 -0.3 to VDD + 0.3 -0.3 to VVFIRE + 0.3 -0.3 to 35
V V V V V
VESD1 VESD2 VFPULSE
2000 200 V 35 25 25
Notes 1. Absolute maximum ratings indicate limits beyond which damage to the device may occur. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 3. 4. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). With a nominal squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. The individual squib driver thermal shutdown will not affect other squib driver firing "ON" times. With a shorted squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. When the thermal shutdown limit is exceeded, the FET driver will turn OFF and the thermal status bit will be set to 1. The FET squib driver can be activated through the arm/fire command when the TEMPRENABLE (MIN) is reached (thermal shutdown status "0"). Nominal squib load is 2.15 0.15 . Shorted squib load is 0.1 . Three-squib driver with RSQUIB = 0.1 conditions. Remaining squib driver conditions: RSQUIB = 1.2 , tON = 4.0 ms, ISQUIB = 2.0 A, VVDIAG_X = VVFIRE_XX = 35 V. Lead soldering temperature limit is for 10 seconds maximum duration; not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Operating ratings indicate conditions for which the device is intended to be functional. For guaranteed specifications and test conditions, refer to the static and dynamic electrical characteristics tables on the following pages.
5. 6. 7.
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Analog Integrated Circuit Device Data Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INPUT VOLTAGE (VDD) Input Voltage FET DRIVERS Leakage Current at Minimum High Side Driver Breakdown Voltage Leakage Current at Minimum Low Side Driver Breakdown Voltage High-Side Driver Current Limit Range Set via Rlimit Resistor with Low Battery Condition tON 4.0 ms, RR_LIMIT_X = 10 k, 5.0 V VVFIRE 7.0 V, RSQUIB = 2.0 High-Side Driver Low Current Limit Range Set via Rlimit Resistor tON 2.6 ms, RR_LIMIT_X = RL=4.32 k, 7.0 V VVFIRE 35 V High-Side Driver Nominal Current Limit Range Set via Rlimit Resistor tON 2.6 ms, RR_LIMIT_X = RL=10 k, 7.0 V VVFIRE 35 V High-Side Driver High Current Limit Range Set via Rlimit Resistor tON 0.8 ms, RR_LIMIT_X = RL=45.3 k, 7.0 V VVFIRE 35 V Low-Side Drivers Current Limit 7.0 V = SQLO < 16 V SQLO = 16 V High-Side Driver Current Limit Detect Threshold (8) 7.0 V VVFIRE 35 V Driver ON Resistance (per FET) VVFIRE = 5.0 V, ILOAD = 0.5 A VDD Operating Current Standby (Diagnostics off, SPI "OFF") No Fire--Worst Case Diagnostics ($83/$2F Command Active) Firing (with All FET Drivers "ON") VFIRE Quiescent Current (9) With Diagnostics Off VDIAG Current During Squib Diagnostics With Squib Resistance Diagnostics Active VFIRE Operating Current During Firing Excluding Firing Current, IHS = 2.0 A VDIAG Operating Current During Firing Per VDIAG terminal, excluding Firing Current, IHS = 2.0 A Notes 8. Guaranteed by design 9. VFIRE quiescent current includes any leakage current through squib. 33797 IRRE - 140 200 IRRE - 1.8 10 A IRRE 32 37 43 mA IRRE 22 34 55 mA IDD - - - 2.0 15 4.3 5.0 17.5 6.0 A RDS(ON) - - 1.0 mA IMEAS IHS x 0.85 - IHS x 1.0 ILS 2.1 2.24 2.47 2.65 3.0 3.14 A IHS(HISET) 1.76 2.0 2.24 A IHS(NOM) 1.21 1.4 1.54 A IHS(LOSET) 0.81 0.93 1.03 A IDHSD IDLSD IHS(LBAT) 1.09 1.4 2.9 A - - 39 65 100 100 A A A VDD 4.57 5.0 5.25 V Symbol Min Typ Max Unit
6
Analog Integrated Circuit Device Data Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VFIRE1A / VFIRE2A Current During High Side Safing Sensor Diagnostics (Command $CO) Per VFIREXA terminal, with High Side Safing Sensor Diagnostic active VFIRE1B / VFIRE2B Current During High Side Safing Sensor Diagnostics (Command $CO) Per VFIREXB terminal, with High Side Safing Sensor Diagnostic active VFIRE1B / VFIRE2B Current During VFIRE Diagnostics (Command $C5) Either VFIRE!B or VFIRE2B Diagnostic active VFIRE Quiescent Current - Total All VFIRE terminals measured together, with Diagnostics Off Maximum Allowable External Capacitance to Ground (10) Per Squib terminal SQB_LO and SQB_HI Maximum Allowable External Resistance to Ground During Firing (10) VFIRE_RTN terminal to Ground Individual FET Driver Thermal Shutdown (10), (11) FET Driver Thermal Shutdown Re-Enable Threshold After Drive Cool-down
(10), (11)
Symbol IRRE
Min
Typ
Max
Unit A
260 IRRE 22 IRRE 0.3 IQVFIRETOTAL 90 CSMAX - RSMAX - TSD TREN 160 90
350
400 A
32 2.0 135
55 mA 3.8 A 180 F
-
0.12
- - -
0.15 190 110 C C
FET DRIVERS HIGH- AND LOW-SIDE DRIVER TRANSISTOR STATUS/DIAGNOSTICS ($82, $83 COMMANDS) Voltage Transistor Test Threshold for High-Side Driver Transistor High-Side Driver Current Limit During High-Side Driver Transistor Diagnostics 15 V VVFIRE_XX 35 V Voltage Transistor Test Threshold for Low-Side Driver Transistor Low-Side Driver Current Limit During Low-Side Driver Transistor Diagnostics 15 V VVFIRE_XX 35 V FEN INPUT TERMINAL (FEN_1 AND FEN_2) Internal Current Pull-Down Logic Low Level Fire Enable Terminal Logic High Level IFEN VFEN(LO) VFEN(HI) -25 0.0 0.65 x VDD -40 2.5 2.5 -50 0.35 x VDD 1.0 x VDD A V V VTRANTST2 ITRANTST2 2.0 10 50 1.0 1.4 2.0 V mA VTRANTST1 ITRANTST1 2.0 10 50 5.5 6.0 6.5 V mA
Notes 10. Guaranteed by design. 11. With a nominal squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. The individual squib driver thermal shutdown will not affect other squib driver firing ON times. With a shorted squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. When the thermal shutdown limit is exceeded, the FET driver will turn OFF and the thermal status bit will be set to 1. The FET squib driver can be activated through the arm/fire command when the TEMPRENABLE (MIN) is reached (thermal shutdown status "0"). Nominal squib load: 2.15 0.15 . Shorted squib load: 0.1 .
33797
Analog Integrated Circuit Device Data Freescale Semiconductor
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic RST INPUT TERMINAL (ACTIVE LOW) (12) System Reset Threshold Internal Current Pull-Down RST Logic Low Level RST Logic High Level SQUIB DIAGNOSTICS ($D0-$D3 COMMANDS) (13) Diagnostic Current Through Squib (14) Resistance Threshold 1 (14) Resistance Threshold 2 (14) Resistance Threshold 3 (14) Resistance Threshold 4 (14) Resistance Threshold 5
(14)
Symbol
Min
Typ
Max
Unit
VDDRST IRST VRST(LO) VRST(HI)
- -6 0.0 0.65 x VDD
- -10 2.5 2.5
4.1 -15 0.35 x VDD 1.0 x VDD
V A V V
IDIAG RTH1 RTH2 RTH3 RTH4 RTH5 RTH6 RTH7 RTH8
30 1.2 1.6 2.1 2.6 3.3 4.6 5.7 6.7
34 1.4 1.8 2.4 2.9 3.7 5.4 6.5 7.8
40.5 1.6 2.1 2.6 3.2 4.4 6.0 7.1 8.5
mA
Resistance Threshold 6 (14) Resistance Threshold 7
(14)
Resistance Threshold 8 (14)
SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTICS AND SQUIB HARNESS SHORT-TO-BATTERY/GROUND DIAGNOSTICS WITH AN OPEN SQUIB ($C1, $C3 COMMANDS) Voltage Threshold for SQB_LO and SQB_HI Shorted to VPWR 7.0 V VVDIAG_X 35 V Voltage Threshold for SQB_LO and SQB_HI Shorted to Ground 7.0 V VVDIAG_X 35 V Current Sink Shorts Measurements I_SQB_LO_XX (15) 1.0 V SENSE_XX 16 V, Typical = 800 A Current Source Shorts Measurements I_SQB_HI_XX (15) 1.0 V SENSE_XX 16 V, 7.0 V VVDIAG_X 35 V Voltage Threshold for SQB_LO or SQB_HI Shorted to VPWR with an Open Squib using $C3 Command RSQUIB = Open Notes 12. Reset Bar range of operation: The minimum system reset bar threshold/active will be set to "0" for a value of VDD 4.1 V. 13. By changing the R_DIAG resistor value, the resistance thresholds can be varied in a linear relationship.The R_DIAG resistance can be changed by 10% to shift the thresholds by 10%. Design goal for resistance threshold change is 15%. R_DIAG threshold limit may have to be changed to accommodate 15% change. Example: Shifting the R_DIAG resistance value 10%, the resistance threshold will change by 10%. Refer to Table 4, page 11. RR_DIAG = 10 k 1.0% XX = 1A, 1B, 2A, or 2B. VTHSB_SO ISOURSHRTS 1.7 5.75 3.5 - 3.7 6.75 V ISINKSHRTS -500 -800 -900 mA VTHSG 1.3 1.4 1.6 A VTHSB 5.7 6.0 6.4 V V
14. 15.
33797
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Analog Integrated Circuit Device Data Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Voltage Threshold for SQB_LO or SQB_HI Shorted to Ground with an Open Squib using $C3 Command RSQUIB = Open DIAGNOSTICS FOR SQUIB CONTINUITY BETWEEN SENSE_XX AND SQB_LO_XX ($C2 COMMAND) Current Threshold for SQUIB_LO_1A, 1B, 2A, and 2B Continuity Check for Standard and Cross-coupled Conditions ($C2) SQUIB_LO_XXCONT 7.0 V VVDIAG_X 35 V DIAGNOSTICS FOR SQUIB SHORT BETWEEN FIRING LOOPS ($E0-$E3, $E8 COMMANDS) Voltage Threshold for Standard Squib Connection 7.0 V VVDIAG_X 35 V Voltage Threshold for SQUIB_X Shorted to SQUIB_Y (1 or More Shorted Conditions) Short Between Squib Lines (Loops) (SQUIB_XX_SSQB_YY) (17) VDIAG SUPPLY DIAGNOSTICS ($C0 COMMAND) VDIAG Supply Voltage High Threshold VDIAG Supply Voltage Low Threshold VFIRE SUPPLY DIAGNOSTICS VFIRE_1B AND VFIRE_2B ($C5 COMMAND) VFIRE Supply Voltage High Threshold VFIRE Supply Voltage Low Threshold VFDHI VFLO 15 5.7 17 6.5 18.3 7.0 V V VDHI VDLO 15 5.7 17 6.5 18.3 7.0 V V VTHSSQB 1.0 1.4 2.0 VTHSQBNOM 1.0 1.4 2.0 V V
(16)
Symbol VTHSG_SO
Min 1.3
Typ 1.8
Max 2.0
Unit V
ITHSQB CON
150
-
350
mA
VDIAG SUPPLY DIAGNOSTICS VDIAG_1 AND VDIAG_2 (ADDITIONAL VOLTAGE THRESHOLDS) ($C5 COMMAND) VDIAG Supply Voltage Threshold 4 VDIAG Supply Voltage Threshold 3 VDIAG Supply Voltage Threshold 2 VDIAG Supply Voltage Threshold 1 VFIRE_RTN DIAGNOSTICS ($C9 COMMAND) R_RTN1 Short-to-Ground Threshold (Open Ground Connection) R_RTN2 Short-to-Ground Threshold (Open Ground Connection) HIGH-SIDE SAFING SENSOR DIAGNOSTICS ($C0 COMMAND) R_HS Valid Resistor Range 15 V VVDIAG_X 35 V R_HS Open Threshold 15 V VVDIAG_X 35 V Notes 16. XX = 1A, 1B, 2A, or 2B 17. XX and YY = 1A, 1B, 2A, or 2B RHSO 6.1 7.2 9.0 RHS 4.1 5.1 6.1 k k RRTN1 RRTN2 0.15 0.15 - - 0.6 0.6 VVDIAG_X V4 VVDIAG_X V3 VVDIAG_X V2 VVDIAG_X V1 30.2 25.5 20.5 16 32.8 27.7 22.6 18.4 36.2 30.2 25.5 20.5 V V V V
33797
Analog Integrated Circuit Device Data Freescale Semiconductor
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic R_HS Short Threshold VFIRE_XA & VFIRE_XB Current during High Side Safing Test at Open Threshold VFIRE_1A & VFIRE_1B or VFIRE_2A & VFIRE_2B VFIRE_XA & VFIRE_XB Current during High Side Safing Test at Short Threshold VFIRE_1A & VFIRE_1B or VFIRE_2A & VFIRE_2B I1HSS 287 385 436 Symbol RHSS I1HSO 270 360 410 A Min 2.8 Typ - Max 4.1 Unit k A
HIGH-SIDE SAFING SENSOR DIAGNOSTICS WITH 1 SAFING SENSOR IN FIRING PATH CONNECTED TO VFIRE_1A AND VFIRE_2A TERMINALS (GUARANTEED BY DESIGN) ($C0 COMMAND) Total VFIRE_XX Current during High Side Safing Test at Open Threshold VFIRE_1A, VFIRE_1B, VFIRE_2A & VFIRE_2B terminals Total VFIRE_XX Current during High Side Safing Test at Short Threshold VFIRE_1A, VFIRE_1B, VFIRE_2A & VFIRE_2B terminals R_HS Valid Resistor Range 15 V VVDIAG_X 35 V R_HS Open Threshold 15 V VVDIAG_X 35 V R_HS Short Threshold 15 V VVDIAG_X 35 V R_LIMIT RESISTOR DIAGNOSTICS ($C8 COMMAND) R_LIMIT Valid Resistor Range R_LIMIT Open Threshold ("Out of Range Threshold") R_LIMIT Short-to-Ground Threshold ("Out of Range Threshold") Maximum External Capacitance to Ground R_DIAG RESISTOR DIAGNOSTICS ($C8 COMMAND) R_DIAG Valid Resistor Range R_DIAG Open Threshold ("Out of Range Threshold") R_DIAG Short-to-Ground Threshold ("Out of Range Threshold") Maximum External Capacitance to Ground
(18)
I2HSO 574 I2HSS 605 R2HS 1.99 R2HSO 2.93 R2HSS 1.41 1.61 1.99 3.35 4.43 - 2.93 748 892 705 835
A A k
k
k
RRL RRLO RRLS CRL
4.32 60 3.0 -
- 76 3.5 -
45.3 105 4.31 20
k k k pF
RRD RRDO RRDS CRD
8.0 13 3.0 -
- 23 5.4 -
13 60 8.0 20
k k k pF
Notes 18. By changing the R_DIAG resistor value, the resistance thresholds can be varied by a linear relationship.The R_DIAG resistance could be changed by 10% to shift the thresholds by 10%. Design goal for resistance threshold change is 15%. R_DIAG threshold limit may have to be changed to accommodate 15% change. Example: Shifting the R_DIAG resistance value 10%, the resistance threshold will change by 10%. Refer to Table 4.
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Analog Integrated Circuit Device Data Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SERIAL INTERFACE Output Logic Low Level (D0) ISINK = -800 A Output Logic High Level (D0) ISOURCE = 800 A Input Logic Threshold (D1, CS, CLK) D1 Pull-Down Current CLK Pull-Down Current CS Pull-Up Current HI-Z Leakage (D0) VLthr ID1 ICLK ICSBAR IHI-Z VOhigh 0.7 0.35 -6.0 -6.0 10 - - - -10 -10 20 - 1.0 0.65 -15 -15 30 10 x VDD A A A A VOlow 0.0 - 0.2 x VDD x VDD Symbol Min Typ Max Unit
Table 4. Resistance Range vs. R_DIAG
R_DIAG 8.0 k (-20%) 9.0 k (-10%) 10.0 k 11.0 k (+10%) 12.0 k (+20%) 13.0 k (+30%) IDIAG (NOM) 41 RTH1 Min/Max 0.9 / 1.3 RTH2 Min/Max 1.2 / 1.7 RTH3 Min/Max 1.6 / 2.1 RTH4 Min/Max 2.0 / 2.6 RTH5 Min/Max 2.6 / 3.6 RTH6 Min/Max 3.6 / 4.8 RTH7 Min/Max 4.5 / 5.7 RTH8 Min/Max 5.3 / 6.8
38 35 32
1.0 / 1.4 1.2 / 1.6 1.3 / 1.8
1.4 / 1.9 1.6 / 2.1 1.8 / 2.3
1.9 / 2.3 2.1 / 2.6 2.3 / 2.9
2.3 / 2.9 2.6 / 3.2 2.9 / 3.6
2.0 / 4.0 3.3 / 4.4 3.6 / 4.9
4.1 / 5.4 4.6 / 6.0 5.0 / 6.6
5.1 / 6.4 5.7 / 7.1 6.2 / 7.8
6.0 / 7.7 6.7 / 8.5 7.4 / 9.4
29
1.4 / 1.9
1.9 / 2.5
2.5 / 3.1
3.1 / 3.9
3.9 / 5.3
5.5 / 7.2
6.8 / 8.6
8.0 / 10.2
26
1.5 / 2.1
2.1 / 2.7
2.7 / 3.4
3.4 / 4.2
4.2 / 5.8
6.0 / 7.8
7.4 / 9.3
8.7 / 11.1
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Analog Integrated Circuit Device Data Freescale Semiconductor
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SERIAL INTERFACE CLK Cycle Time (1/FCLK) (19) CLK High Time (19) VCLK > VDD x 70% CLK Low Time (19) VCLK < VDD x 20% Clock Rise Time (19) VCLK = 20% VDD to 70% VDD, CLOAD = 100 pF Clock Fall Time (19) VCLK = 70% VDD to 20% VDD, CLOAD = 100 pF Data Out Rise Time (20) VDO = 20% VDD to 70% VDD, CLOAD = 100 pF Data Out Fall Time (20) VDO = 70% VDD to 20% VDD, CLOAD = 100 pF Chip Select Setup Time (20) CSB Before CLK Chip Select Hold Time (20) CLK Before CSB Data In Setup Time (20) D1 Valid Before CLK Data In Hold Time (20) D1 Hold Time After CLK Data Out Access Time (20) CSB to D0 Valid tDIS - tV - tHO 0.0 tDIAG 2.5 - - - - s - 75 ns - 62 ns tA - - 62 ns tH 30 - - ns tSU 30 - - ns tLAG 62 - - ns tLEAD 62 - - ns tF - - 20 ns tR - - 20 ns tFALL - - 20 ns tRISE - - 20 ns tLO 34 - - ns tCYC tHI 34 - - ns 200 - - ns ns Symbol Min Typ Max Unit
Data Out Disable Time (20) CSB to D0 HI-Z Data Out Valid Time (20) CLK to D0 Valid, CLOAD = 100 pF Data Out Hold Time (20) D0 held After CLK Diagnostic Delay Time (Between Two Successive Commands) Notes 19. Determined by Design 20. Guaranteed by Characterization
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Analog Integrated Circuit Device Data Freescale Semiconductor
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k 1%, RR_DIAG = 10 k 1%, -40C TA +85C, GND = 0 unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic FET DRIVERS Turn-On Delay Time CS to 80% IHS Turn-Off Delay Time CS to 20% IHS Diagnostic Timing/Resolution 5.0 V VVDIAG_X 35 V, IHS IMEAS, 0 s tMEASURE_TIME 6.375 ms, CSQUIB_HI = 0.12 F, CSQUIB_LO = 0.12 F DIAGNOSTIC DELAY TIME Squib Resistance Diagnostic Delay Time (21) From CSB Until Transistor Test Results Are Valid, CSQUIB_HI = 0.12 F, CSQUIB_LO = 0.12 F Squib Open/Short Diagnostic Delay Time (21) From CSB Until Squib Open/Short Diagnostic Results Are Valid, CSQUIB_HI = 0.12 F, CSQUIB_LO = 0.12 F VDIAG Supply Diagnostic Delay Time From CSB until VDIAG Diagnostic Results Are Valid
(21)
Symbol
Min
Typ
Max
Unit
tON - tOFF - tRESOLUTION 21.25 25 28.75 - 10 - 72
s
s
s
tDIAG1 - tDIAG2 - tDIAG4 - tDIAG6 - tDIAG7 - tDIAG9 - tDIAG10 - tDIAG11 - tDIAG12 - - 3000 - 3000 - 300 - 1000 - 1000 - 1000 - 3000 - 3000 - 300
s
s
s s
VFIRE Supply Diagnostic Delay Time (21) 15 V VVDIAG_X 35 V, From CSB Until High-Side Safing Sensor Diagnostic Results Are Valid, CVDIAG < 0.015 F High-Side Safing Sensor Diagnostic Delay Time (21) 15 V VVDIAG_X 35 V, From CSB Until High-Side Safing Sensor Diagnostic Results Are Valid, CVDIAG < 0.015 F FET Drivers High- and Low-Side Driver Transistor Diagnostic Delay Time (21) 15 V VVDIAG_X 35 V, From CSB Until Transistor Test Results Are Valid, CSQUIB_HI = 0.12 F, CSQUIB_LO = 0.12 F, CVDIAG < 0.015 F VFIRE_RTN Diagnostic Delay Time (21) From CSB Until VFIRE_RTN Diagnostic Results Are Valid Squib Continuity Diagnostic Delay Time (21) From CSB Until VTHSQBCON Diagnostic Results Are Valid Squib Short Between Firing Loops Diagnostic Delay Time From CSB Until VTHSSQB Diagnostic Results Are Valid (21) FEN INPUT TERMINAL Minimum Pulse Width Notes 21. Guaranteed by Characterization
s
s
s
s
s
FENFILTER
12
14
16
s
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TIMING DIAGRAMS
TIMING DIAGRAMS
Chip Select (/CS) CS
80% IHS 20% tON
Figure 4. Driver Timing Diagram
tOFF
CS
CLK MISO MOSI MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
Figure 5. Freescale SPI
CS
CLK MISO MOSI MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
Figure 6. Alternative SCI Mode
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The Four-Channel Squib Driver IC is a complete squib diagnostic and deployment interface for use in automotive air bag modules. Extensive diagnostics and system control features are incorporated to provide fail-safe operation. The device contains a serial peripheral interface- (SPI) compatible 8-bit interface for microprocessor control. This interface allows the microprocessor to set up and read back the results of all internal diagnostic functions. Squib resistance level, along with possible shorts-to-battery or ground, open ground connections, or shorts between squib firing loops, are included in the diagnostic set. Additionally, the squib supply voltage levels can be checked and the lowside fire return can be checked for an open condition (open ground connection). The SPI interface, along with the additional FEN terminal, is used to arm and fire a selected squib. The device has the capability to be used in a standard fourchannel squib driver IC or in a cross-coupled state with the high- and low-side squib drivers located on separate squib driver ICs. Both the high-side and low-side output drivers are protected against temporary shorts to battery or ground. The current limit threshold is set by an external resistor.
FUNCTIONAL TERMINAL DESCRIPTION INTRODUCTION
In this section references are made to XX; e.g., in SENSE_XX, SQB_LO_XX, and SQB_LO_XX_CONT. In these and similar instances, XX denotes 1A, 1B, 2A, and 2B.
DEVICE GROUND (GND)
Device ground terminal for internal logic and diagnostic circuitry.
SERIAL CLOCK (SCLK)
Serial clock input for SPI interface. Data on the D1 terminal is clocked into the device on the rising edge. Data is clocked out of the device via the D0 terminal on the falling edge. Default state is low with no connection.
DEVICE POWER (VDD)
Device power terminal for internal logic and diagnostic circuitry.
RESET (RST)
Reset Bar. Active low. With low input signal the internal functions of the squib driver IC are disabled and all data in the serial interface shift registers is cleared. Default state is low with no connection.
CHIP SELECT (CS)
Chip select for SPI interface. Active low. On rising edge, data shifted into the shift register is internally latched. On falling edge, diagnostic results are latched into shift register. Default state is high with no connection.
LIMIT RESISTOR - DIAGNOSTIC (R_DIAG)
External resistor to ground is used to set the diagnostic current for squib resistance.
MASTEROUT/SLAVE IN (MOSI)
Serial data input to 33797 SPI interface. Default state is low with no connection.
LIMIT RESISTOR 1A AND 1B (R_LIMIT_1)
External resistor to ground is used to set current limit for squibs 1A and 1B FET drivers.
MASTER IN/SLAVE OUT (MISO)
Serial data output from 33797 SPI interface.
LIMIT RESISTOR 2A AND 2B (R_LIMIT_2)
External resistor to ground is used to set current limit for squibs 2A and 2B FET drivers.
FET DRIVER 1A AND 1B (FEN_1)
Active high input signal to enable operation of squibs 1A and 1B FET drivers. All diagnostic functions are available while terminal is low. Default state is low with no connection.
SQUIB DIAGNOSTIC 1A AND 1B (VDIAG_1)
Diagnostic terminals for the high-side safing sensors for squibs 1A and 1B, as well as the VFIRE supply voltage.
FET DRIVER 2A AND 2B (FEN_2)
Active high input signal to enable operation of squibs 2A and 2B FET drivers. All diagnostic functions are available while terminal is low. Default state is low with no connection.
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FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
SQUIB DIAGNOSTIC 2A AND 2B (VDIAG_2)
Diagnostic terminals for the high-side safing sensors for squibs 2A and 2B, as well as the VFIRE supply voltage.
DESIGN NOTES
Diagnostics always have the form of a forcing function and a measurement or sense function. In a cross couple configuration, most diagnostics are unaffected and are single commands except for $C2 Low Side FET Continuity and $E<3:0> Harness Shorts, and 83/2x Low- Side FET test. This command must be sent to each IC to be executed. For these three diagnostics, two commands are required because the forcing function and sensing function are on separate ICs. Harness Shorts Diagnostics: Force using $E<3:0> on IC#1, Sense $E8 on IC2 Low-Side FET Continuity: Force using $C1 on IC#1, Sense using $C2 on IC#2 Low-Side FET Test: Force using $C1 on IC#1, Sense using $C2 on IC#2 An active 600 A current sink is located in the SENSE_XX terminal. The sink current is used to pull the charge off of the external EMC/filter caps after a diagnostic measurement has been made.
SQUIB SENSE XX (SENSE_XX)
The Sense terminals are used exclusively for diagnostics related to the squib, driver FETs, or harness. Commands using the Sense terminals include: * C1, C2, C3, C9 * D<3:0> * E<3:0> * E9 * 82/1x * 83/2x Independent of the system configuration, normal or cross coupled, the Sense terminal, xx and SquibHi, xx of a single IC are always connected to the same squib with the SquibHi pin connected to the high terminal of the squib and the Sense pin connected to the low terminal of the squib. A cross coupled configuration is achieved by only cross coupling the squib low pins. See Figure 7 and Figure 8.
SQUIB HI XX (SQB_HI_XX)
Squib high terminals for squibs 1A, 1B, 2A, and 2B. These terminals are connected to the sources of the high-side FET drivers, as well as the diagnostic circuitry.
STANDARD APPLICATIONS
In the standard mode, the $C2 (SQUIB_LO_XX_CONT) command will be used to check continuity of the low-side driver from the SQB_LO_XX terminal to the high-side driver FET (see Figure 7).
SQUIB LOW XX (SQB_LO_XX)
Squib low terminals for squibs 1A, 1B, 2A, and 2B. These terminals are connected to the drains of the low-side FET drivers, as well as the diagnostic circuitry.
CROSS-COUPLED APPLICATIONS
Used during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). SENSE_XX terminals from squib driver IC #1 are connected to their respective squib minus terminals (Squib Low/SQB_LO_XX) from squib driver IC #2 (Figure 8). SENSE_XX terminals are used to feed diagnostic signals back to squib driver IC #1 for determining squib resistance, short-to-battery/ground, and squib loop-to-loop short conditions. During a fire event, the fire current passes from squib driver IC #1 high-side driver though the squib to squib driver IC #2 low-side driver (Figure 8). In the cross-coupled mode, the squib driver IC #2 $C2 (SQUIB_LO_XX_CONT) command will be used to check continuity of the low-side driver from the SQB_LO_XX terminal to the low-side driver FET.
SQUIB FIRING SUPPLY XX (VFIRE_XX)
Firing supply terminals for squibs 1A, 1B, 2A, and 2B. These terminals are connected to the drains of the high-side FET drivers. Feedback for high-side safing for squibs 1A and 1B will be referenced from VFIRE_1A and squibs 2A and 2B from VFIRE_2A. For high-side safing, VFIRE_1B should be connected to VFIRE_1A terminal and VFIRE_2B to VFIRE_2A terminal.
SQUIB FIRE POWER GROUND (VFIRE_RTN)
Return for squibs 1A, 1B, 2A AND 2B. The terminals are tied to the source terminals of both low-side FET drivers, as well as the diagnostic circuitry. The RTN terminals are tied internally.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
VBOOST VFIRE Dri ver Control 1A +
CS1 SPI Interface
SENSE_1A -
Squib 1
SQUIB IC #1
$C2 Command checks this
Figure 7. Standard Squib Firing
VBOOST VFIRE Dri ver Control 1A
+ Squib 1 SENSE_1A Squib 2
CS1 SPI Interface CS2
SQUIB ASIC #1 VFIRE Dri ver Control
+ SENSE_1A -
SQUIB ASIC #2
$C2 Command checks this
Figure 8. Cross-Coupled Squib Firing
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTRODUCTION
In this section references are made to XX; e.g., in SQB_HI_XX, SQB_LO_XX, and SENSE_XX terminals. SQB_HI_XX refers to SQB_HI_1A, SQB_HI_1B, SQB_HI_2A or SQB_HI_2B, SQB_LO_1A, etc. 7 is set to a "0". When a $C8 command is issued for the twochannel squib driver IC, the response bit 7 is set to a "1".
STANDARD SQUIB IC FUNCTION
The standard squib IC application utilizes the high- and low-side squib drivers from the same squib driver ICs (see Figure 7, Standard Squib Firing). The SENSE_XX (1A, 1B, 2A, 2B) terminal is connected to SQB_LO_XX (1A, 1B, 2A, 2B). Squib diagnostics are conducted using this terminal. In the standard mode, the $C2 (SQUIB_LO_XX_CONT) command will be used to check continuity of the low-side driver from the SQB_LO_XX terminal (1A, 1B, 2A, 2B) to the low-side driver FET (Figure 7). The low-side driver continuity is checked during the continuity test. The driver continuity information will be cleared after the information is transmitted on the next valid SPI command.
SERIAL INTERFACE
An 8-bit shift register is provided for communication through the serial port to a microprocessor. The four-wire SPI interface is used to read from, and write to, the shift register. Data written to the shift register will control the firing of the FET switches or select a diagnostic mode. Data is sequentially shifted into and out of the shift register, most significant bit first. Data read from the shift register will contain the results of the diagnostic mode selected in the previous 8-bit write. If a NOP command is written, all diagnostic modes are cleared and the data in the shift registers will be read out. With any undefined commands, all diagnostic modes are cleared and the data in the shift registers will be read out. All functions are set when CS goes high. All diagnostic commands are cleared on the next valid SPI command.
EXAMPLE--STANDARD SQUIB COMMAND SPI SEQUENCE FROM MICROCONTROLLER
TX: Request squib short-to-battery/GND diagnostic measurement ($C1). RX: Previous executed command information. TX: Request squib 1A resistance measurement ($D0- $D3). RX: Receive results from short-to-battery/GND diagnostics. TX: Request squib 1B resistance measurement ($D0- $D3). RX: Receive measured squib 1A resistance information. TX: Request squib 2A resistance measurement ($D0- $D3). RX: Receive measured squib 1B resistance information. TX: Request squib 2B resistance measurement ($D0- $D3). RX: Receive measured squib 2A resistance information TX: Request continuity command ($C2). RX: Receive measured squib 2B resistance information TX: Request another command sequence. RX: Receive low-side driver 1A, 1B, 2A, and 2B continuity information. Latches will be cleared after data transferred from the squib IC (clear on rising edge of chip select).
SPI INTERFACE INTEGRITY CHECK
The $96 command with corresponding $69 return byte during the next 8-bit write is used as an echo function to diagnose the SPI integrity (refer to Table 8). The Diagnostic Data Out bits not containing data are set to zero. Only 8-bit words will be accepted. Any words that are 7 bits or 9 bits will be ignored or cleared. The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands must be sequential or they will be treated as a NOP. The four-channel squib driver IC is a slave peripheral device designed to interface to a Freescale SPI or other serial peripheral interface. Data is read on the rising edge of CLK, and data is transferred out on the rising edge of CLK. On the falling edge of CSB, the IC configures itself for one of two SPI modes. If CLK is low, the IC will configure itself to be in Freescale SPI mode (see Figure 5). If CLK is high, the IC will configure itself to be in an alternative SCI mode (see Figure 6). In both cases, data is still read off the rising edge and transferred off the falling edge of the CLK. When the IC is deselected (CSB goes high), then D0 is a high-impedance output. Response bit 7 of command $C8 (refer to Table 7, page 22) is hard-wired to "1" or "0" to identify the squib IC as a four- or two-channel squib driver IC. When a $C8 command is issued for the four-channel squib driver IC, the response bit
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
TX: Request loop-to-loop short command ($E0-$E3) RX: Previous executed command information. TX: Request another command sequence. RX: Receive loop-to-loop results from test.
EXAMPLE--CROSS-COUPLED SQUIB COMMAND SPI SEQUENCE FROM MICROCONTROLLER
TX: Squib IC #1 request squib 1A resistance measurement ($D0). RX: Previous executed command information. TX: Run another command on the same squib IC #1. RX: Receive measured squib 1A resistance information. TX: Squib IC #1 request continuity command ($C2). RX: Previous executed command information. TX: Squib IC #2 request continuity command ($C2). RX: Previous executed command information. TX: Squib IC #2 request continuity command ($C2). RX: Receive low-side driver continuity information for lowside drivers which reside on IC #2. TX: Squib IC #1 request another command sequence. RX: Receive low-side driver continuity information for lowside drivers that reside on IC #1. TX: Squib IC #1 request loop-to-loop short command ($E0-$E3) RX: Previous executed command information. TX: Squib IC #2 request loop to loop short command for other ICs ($E8). RX: Previous executed command information. TX: Squib IC #2 request loop-to-loop short command for other ICs ($E8). RX: Receive loop-to-loop results from test run on IC #1. TX: Squib IC #1 request another command sequence. RX: Receive loop-to-loop results from test run on IC #1.
CROSS-COUPLED SQUIB IC FUNCTION
The cross-coupled application utilizes the high- and lowside squib drivers from two different squib driver ICs (see Figure 8, Cross-Coupled Squib Firing, page 17.) Through the SPI interface, the squib IC will maintain the capability to conduct standard diagnostics (short-to-battery, short-toground, short between squibs, and squib diagnostics) between two different squib ICs. The squib IC must maintain the capability to fire the squib drivers with the ARM and FIRE command in either cross-coupled or single IC applications. When the firing squib driver IC is used in cross-coupled applications, the low-side squib driver must be activated prior to activating the high-side squib driver. Cross-coupling the high- and low-side squib driver from two different squib driver ICs must be done without interfering with standard squib operations when the squib IC is used in an application where the high- and low-side squib drivers are located on the same IC. All remaining diagnostic functions will operate standard in either a cross-coupled or single IC applications. These functions include RR_DIAG, RR_LIMIT_X, High side, VVFIRE_XX, VVFIRE_RTN, VTRANSTX, squib current timing measurement, and FEN_1 and FEN_2 diagnostics. The SENSE_1A (1B, 2A, or 2B) terminal squib IC #1 is connected to SQB_LO_1A (1B, 2A, or 2B) terminal squib driver IC #2 and is used to feed the diagnostic signal for determining squib resistance and short-to-battery/ground conditions (see Figure 8, page 17). During a fire event, the fire current passes from squib driver IC #1 high-side driver though the squib to squib driver IC #2 low-side driver. In the cross-coupled mode, the squib driver IC #2 $C2 (SQUIB_LO_1A_CONT, [1B, 2A, or 2B]) command will be used to check continuity of the low-side driver from the SQB_LO_1A (1B, 2A, or 2B) terminal to the low-side driver FET. The low-side driver continuity is checked during the continuity test. The driver continuity information will be cleared after the information is transmitted on the next valid SPI command.
FIRING A SQUIB
The firing of a squib driver requires the FEN_1 and FEN_2 terminals to be high and two separate 8-bit writes be made to the shift register. With FEN_1 terminal high, squibs 1A and 1B can be armed and fired. With FEN_2 terminal high, squibs 2A and 2B can be armed and fired. The first write is to ARM squib drivers in preparation of receiving the fire command. Squib 1A and squib 1B can be armed separately from squib 2A and squib 2B (refer to Table 6) or all squibs can be fired at once (refer to Table 7). All ARM and 5X (Fire) commands will be echoed back on the SPI Data output.
Table 6. Squib Firing Commands
Hex Code A0 ARM Squib Drivers 1A and 1B A1 ARM Squib Drivers 2A and 2B Command Description
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Table 6. Squib Firing Commands
Byte #1 Byte #2 A0 A1 A2 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON Squib B High Side Squib B Low Side Squib A High Side Squib A Low Side Squib 2B Squib 2A Squib 1B Squib A1
ARM Squib Drivers 1A and 1B ARM Squib Drivers 2A and 2B ARM Squib Drivers 1A, 1B, 2A, 2B OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON
The second write is to actually fire the desired driver. The four most significant bits of the second write are used to establish a parity with the four most significant bits of the first write. The four least significant bits are the data bits, and each bit represents a squib driver or squib driver pair. If there is a parity mismatch of the four most significant bits, the data bits will be ignored and the squib drivers will not have their status changed. The 2-byte write sequence must then be started again. During the first write, when the drivers are armed, all diagnostic functions are cleared. Once fired, a driver can only be turned off by one of the following: * Sending a valid 2-byte write sequence through the shift register. * Having the reset terminal pulled low.
* Having the thermal shutdown limit exceeded (once minimum firing duration requirement has been met; refer to Note 4 in the Maximum Ratings table, page 5). * Having the FEN terminal pulled low. Note that the code sequences allow any combination of drivers to be turned on or off. Once fired, the current limit measurement register increments when the squib current is measured and is above the IMEAS threshold during the timer activation. The FEN_1 or FEN_2 terminal must be high to enable firing of the drivers. If fire command is active and the FEN (1 or 2) terminal is pulled low, the FET drivers will turn off (assuming the latch and hold function is not in effect; refer to paragraph entitled FEN_1 and FEN_2, page 28). If fire command is active and the FEN (1 or 2) terminal is pulled high, the FET driver will turn on.
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
During the firing of a squib, significant I*R losses may occur, which could cause a voltage shift across a circuit board trace. It is recommended that current paths for Table 7. Diagnostic Bit Definitions
Hex Code 00 70 Command Description NOP Squib 1A Current Measurement Time Squib 1B Current Measurement Time Squib 2A Current Measurement Time Squib 2B Current Measurement Time Squib X Current Status
discharging the firing supply storage capacitors through the squib be kept as short as possible and isolated from logic and diagnostic grounds.
Diagnostic Data Out (Available on Next Command) Bit 7 0 SQB_1A BIT 7 MS SQB_1B BIT 7 MS SQB_2A BIT 7 MS SQB_2B BIT 7 MS 0 Bit 6 0 SQB_1A BIT 6 Bit 5 0 SQB_1A BIT 5 Bit 4 0 SQB_1A BIT 4 Bit 3 0 SQB_1A BIT 3 Bit 2 0 SQB_1A BIT 2 Bit 1 0 SQB_1A BIT 1 Bit 0 0 SQB_1A BIT 0 LS SQB_1B BIT 0 LS SQB_2A BIT 0 LS SQB_2B BIT 0 LS
71
SQB_1B BIT SQB_1B BIT 6 5
SQB_1B BIT 4
SQB_1B BIT 3
SQB_1B BIT 2
SQB_1B BIT 1
72
SQB_2A BIT 6
SQB_2A BIT 5
SQB_2A BIT 4
SQB_2A BIT 3
SQB_2A BIT 2
SQB_2A BIT 1
73
SQB_2B BIT 6
SQB_2B BIT 5
SQB_2B BIT 4
SQB_2B BIT 3
SQB_2B BIT 2
SQB_2B BIT 1
79
0
0
0
SQB_2B SQB_2A SQB_1B SQB_1A Current Limit Current Limit Current Limit Current Limit Status Status Status Status Thermal LSDSTAT _1B RSSLO Thermal HSDSTAT _1B RSSHI Thermal LSDSTAT _1A VDIAG _1 VDHI Thermal HSDSTAT _1A VDIAG _1 VDLO
7F
Thermal Shutdown Status ThermalSD VDIAG and HighSide Safing Sensor Diagnostics Squib Short-toGround/Short-toBattery Diagnostics Low-Side Driver Continuity Status Harness Short-toGround/ Short-toBattery with Squib Open (No Squib Present) Command Description VFIRE_1B and VFIRE_2B Voltage
Thermal LSDSTAT _2B RSSLO
Thermal HSDSTAT _2B RSSHI
Thermal LSDSTAT _2A VDIAG _2 VDHI
Thermal HSDSTAT _2A VDIAG _2 VDLO
C0
C1
SQB_2B NO_SH_ GND
SQB_2B NO_SH_ BATT
SQB_2A NO_SH_ GND
SQB_2A NO_SH_ BATT
SQB_1B NO_SH_ GND
SQB_1B NO_SH_ BATT
SQB_1A NO_SH_ GND
SQB_1A NO_SH_ BATT
C2
0
0
0
0
SQB_LO_2B_ SQB_LO_2A SQB_LO_1B SQB_LO_1A CONT CONT CONT CONT SQB_1B OPEN NO_SH_ GND SQB_1B OPEN NO_SH_ BATT SQB_1A OPEN NO_SH_ GND SQB_1A OPEN NO_SH_ BATT
C3
SQB_2B OPEN NO_SH_ GND
SQB_2B OPEN NO_SH_ BATT
SQB_2A OPEN NO_SH_ GND
SQB_2A OPEN NO_SH_ BATT
Hex Code C5
Diagnostic Data Out (Available on Next Command) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 VFIRE _B Tested Bit 3 X Bit 2 X Bit 1 VHI Bit 0 VLO
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Table 7. Diagnostic Bit Definitions (continued)
C6 VDIAG_1 and VDIAG_2 Diagnostics FEN Status, R_LIMIT_X, R_DIAG Status, IC Type VFIRE_RTN Status (Open Ground) Squib 1A Resistance Squib 1B Resistance Squib 2A Resistance Squib 2B Resistance Shorts Between Squib Loops, Squib 1A Shorts Between Squib Loops, SQUIB 1B Shorts Between Squib Loops, Squib 2A Shorts Between Squib Loops, Squib 2B Shorts Between Squib Loops, for Additional ICs VDIAG_2 V4 VDIAG_2 V3 VDIAG_2 V2 VDIAG_2 V1 VDIAG_1 V4 VDIAG_1 V3 VDIAG_1 V2 VDIAG_1 V1
C8
1
R_LIMIT_2 NO_FAULT
R_LIMIT_1 NO_FAULT
R_DIAG NO_ FAULT
FEN 2 Latch Status
FEN 1 Latch Status
FEN 2 Status
FEN 1 Status
C9
0
0
0
0
0
0
VFIRE_ RTN_2 VF2LOW SQB_1A RC2 SQB_1B RC2 SQB_2A RC2 SQB_2B RC2 SQB_1B SQB_1A
VFIRE_ RTN_1 VF1LOW SQB_1A RC1 SQB_1B RC1 SQB_2A RC1 SQB_2B RC1 SQB_1A
D0
SQB_1A RC8 SQB_1B RC8 SQB_2A RC8 SQB_2B RC8 0
SQB_1A RC7 SQB_1B RC7 SQB_2A RC7 SQB_2B RC7 0
SQB_1A RC6 SQB_1B RC6 SQB_2A RC6 SQB_2B RC6 0
SQB_1A RC5 SQB_1A RC4
SQB_1A RC3 SQB_1B RC3 SQB_2A RC3 SQB_2B RC3 SQB_2A SQB_1A
D1
SQB_1B RC5 SQB_1B RC4
D2
SQB_2A RC5 SQB_2A RC4
D3
SQB_2B RC5 SQB_2B RC4
E0
0
SQB_2B SQB_1A
E1
0
0
0
0
SQB_2B SQB_1B
SQB_2A SQB_1B
SQB_1B
SQB_1A SQB_1B
E2
0
0
0
0
SQB_2B SQB_2A
SQB_2A
SQB_1B SQB_2A
SQB_1A SQB_2A
E3
0
0
0
0
SQB_2B
SQB_2A SQB_2B
SQB_1B SQB_2B
SQB_1A SQB_2B
E8
0
0
0
0
SQB_2B SHORT
SQB_2A SHORT
SQB_1B SHORT
SQB_1A SHORT
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Table 8. Command Programming and Diagnostic Bit Definitions
Hex Code 3X Command Description Current Measurement Register Reset Command for Squib X Current 1=ON DATA OUT Squib X Current Register Reset Status 80 Unlock for FEN 1 Counter Registers Programming. Response DATA Output: Command Echoed XX Programming Command for FEN 1 Counter 1=ON Response DATA OUT FEN 1 Counter Programming Status 81 Unlock for FEN 2 Counter Registers Programming Response DATA Output: Command Echoed Command Programming Input and Diagnostic Data Out (Available on Next Command) (22) Bit 7 0 Bit 6 0 Bit 5 1 Bit 4 1 Bit 3 SQB_2B Data/Timer Reset Bit 2 Bit 1 Bit 0
SQB_2A SQB_1B SQB_1A Data/Timer Data/Timer Data/Timer Reset Reset Reset
0
0
1
1
SQB_2B Data/Timer Reset
SQB_2A SQB_1B SQB_1A Data/Timer Data/Timer Data/Timer Reset Reset Reset
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
FEN1 CNT BIT 7 MSB
FEN1 CNT BIT 6
FEN1 CNT BIT 5
FEN1 CNT BIT 4
FEN1 CNT BIT 3
FEN1 CNT BIT 2
FEN1 CNT BIT 1
FEN1 CNT BIT 0 LSB
FEN1 CNT BIT 7 MSB
FEN1 CNT BIT 6
FEN1 CNT BIT 5
FEN1 CNT BIT 4
FEN1 CNT BIT 3
FEN1 CNT BIT 2
FEN1 CNT BIT 1
FEN1 CNT BIT 0 LSB
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
Notes 22. The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP.
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Table 8. Command Programming and Diagnostic Bit Definitions (continued)
Hex Code XX Command Description Programming Command for FEN 2 Counter 1=ON Response DATA OUT FEN 2 Counter Programming Status 82 Unlock to Test High-Squib Drivers 1A, 1B, 2A, 2B Response DATA Output: Command Echoed 1X High-Side Driver Transistor Test Command Response DATA OUT High-Side Driver Transistor Status VTRANTST1 83 Unlock to Test Low Squib Drivers 1A, 1B, 2A, and 2B Response Data Output: Command Echoed 2X Low-Side Driver Transistor Test Command Response DATA OUT Low-Side Driver Transistor Status VTRANTST2 FEN2 CNT BIT 7 MS FEN2 CNT BIT 6 FEN2 CNT BIT 5 FEN2 CNT BIT 4 FEN2 CNT BIT 3 FEN2 CNT BIT 2 FEN2 CNT BIT 1 FEN2 CNT BIT 0 LS Command Programming Input and Diagnostic Data Out (Available on Next Command) (23) Bit 7 FEN2 CNT BIT 7 MS Bit 6 FEN2 CNT BIT 6 Bit 5 FEN2 CNT BIT 5 Bit 4 FEN2 CNT BIT 4 Bit 3 FEN2 CNT BIT 3 Bit 2 FEN2 CNT BIT 2 Bit 1 FEN2 CNT BIT 1 Bit 0 FEN2 CNT BIT 0 LS
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
1
SQB_ 2B High-Side Driver "ON" SQB_2B
SQB_ 2A SQB_1B SQB_1A High-Side High-Side High-Side Driver "ON" Driver "ON" Driver "ON" SQB_2A SQB_1B SQB_1A
0
0
0
0
HSDSTAT_2B HSDSTAT_2A HSDSTAT_1B HSDSTAT_1A
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
0
SQB_ 2B Low-Side Driver "ON" SQB_2B
SQB_2A SQB_1B SQB_1A Low-Side Low-Side Low-Side Driver "ON" Driver "ON" Driver "ON" SQB_2A SQB_1B SQB_1A
0
0
0
0
LSDSTAT_ 2B LSDSTAT_ 2A LSDSTAT_1B LSDSTAT_1A
Notes 23. The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP. Hex Code Command Description Command Programming Input and Diagnostic Data Out (Available on Next Command) (24) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Table 8. Command Programming and Diagnostic Bit Definitions (continued)
90 Reserved for Freescale Read NVM Low Reserved for Freescale Read NVM High Reserved for Freescale NVM Enable Reserved for Freescale Test Mode Enable SPI Integrity Check Response DATA OUT: $69 Echo to Diagnose the SPI Integrity X X X X X X X X
91
X
X
X
X
X
X
X
X
92
X
X
X
X
X
X
X
X
93
X
X
X
X
X
X
X
X
96
1 0
0 1
0 1
1 0
0 1
1 0
1 0
0 1
Notes 24. The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP.
PROTECTION AND DIAGNOSIS FEATURES
The diagnostic circuit's internal references are provided by a bandgap voltage reference, and by scaled currents determined by the resistor value of R_DIAG and the value of the bandgap voltage. Refer to Table 7, Diagnostic Bit Definitions, and Table 8, Command Programming and Diagnostic Bit Definitions, as necessary throughout this section.
HIGH-SIDE SAFING SENSOR DIAGNOSTICS ($C0 COMMAND)
This function monitors the VFIRE_XX terminal connection to the VDIAG_X terminal. The high-side safing function is attached to the VFIRE _1A and VFIRE_2A terminals. The high-side safing function is not available on the VFIRE _1B and VFIRE_2B terminals. When enabled, this diagnostic circuit will typically draw less than 500 A from the VFIRE supply voltage source. Internal window comparators will monitor the voltage difference between the VDIAG_X terminal and the VFIRE_XX terminal, and will provide two bits of data to indicate if the terminal voltage is either above (open) or below (shorted) the threshold levels. When using a high-side safing sensor, typical 5.1 k reference resistor must be placed across the sensor to provide a current path for the diagnostic circuit. As long as there is a current path and the safing sensor switch is open, the resulting differential voltage will fall between the comparator thresholds so that neither an open fault nor a shorted fault condition will be indicated. A closed safing sensor will be indicated as a short, and a loss of the connection between the VDIAG_X terminal and the VFIRE_XX terminal will be indicated as an open. Any external capacitance on the VFIRE_XX terminal will affect the time needed to settle to an accurate value.
R_DIAG and R_LIMIT_X RESISTOR DIAGNOSTICS ($C8 COMMAND)
This function monitors reference currents derived by the R_LIMIT_1, R_LIMIT_2, and R_DIAG resistors. An open terminal or short to ground will cause the comparator to give an "out of range resistor value" indication. A short to VDD will have the same effect as an open terminal and will cause an "out of range resistor value" indication.
R_LIMIT_X and R_DIAG DATA RESULTS
If R_LIMIT_X is open, shorted to ground, or shorted to VDD, the bit R_LIMIT_NO_FAULT will be set to "0". Standard operation will have this bit set to "1". If R_DIAG is open, shorted to ground, or shorted to VDD, the bit R_DIAG_NO_FAULT will be set to "0". Standard operation will have this bit set to "1". The FEN 1 and FEN 2 status bits are a reflection of the FEN_1 and FEN_2 terminals.
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FUNCTIONAL DESCRIPTION PROTECTION AND DIAGNOSIS FEATURES
HIGH-SIDE SAFING SENSOR DIAGNOSTIC DATA RESULTS
If the VFIRE_XX terminal is shorted to the VDIAG_X terminal, the RSSLO bit will be set to "1" and the RSSHI bit will be set to "1". If the VFIRE_XX terminal has no connection to the VDIAG_X terminal, the RSSLO bit will be set to "0" and the RSSHI bit will be set to "0". Standard operation with a safing sensor resistor will have the RSSHI bit set to "1" and the RSSLO bit set to "0".
the predetermined threshold levels. There is one diagnostic circuit for each VDIAG_X terminal.
VDIAG_X VOLTAGE DIAGNOSTIC DATA RESULTS If the VDIAG_X voltage is above the threshold limit, the
VDIAG_X VX bit will be set to "1". If the VDIAG_X voltage is below the threshold limit, the VDIAG_X VX bit will be set to "0".
FIRING SUPPLY VOLTAGE (VDIAG_X) DIAGNOSTICS ($C0 COMMAND)
This function monitors the voltage on the VDIAG_X terminal. The supply voltage is compared to two thresholds (nominal and minimum) and will provide two bits of data to indicate if the terminal voltage is above, below, or in between the predetermined threshold levels. There is one diagnostic circuit for each VDIAG_X terminal.
VFIRE_RTN DIAGNOSTICS ($C9 COMMAND)
This function monitors the resistance on the VFIRE_RTN terminal for open terminal connections. The VFIRE_RTN voltage is compared to a threshold to determine if the VFIRE_RTN terminal connection between the terminal and the printed circuit board is shorted or open.
VFIRE_RTN DIAGNOSTIC DATA RESULTS
If the VFIRE_RTN terminal is above the threshold limit (open), the VFIRE_RTN X VFXLOW will be set to "1". If the VFIRE_RTN terminal is below the threshold limit (shorted), the VFIRE_RTN X VFXLOW will be set to "0". VFIRE return tests are disabled during firing.
VDIAG_X SUPPLY VOLTAGE DIAGNOSTIC DATA RESULTS
If the VDIAG_X voltage is above the high limit, bits VDHI and VDLO will both be set to "1". If the VDIAG_X voltage is between the high limit and the low limit, bit VDHI will be set to "0" and VDLO will be set to "1". If the VDIAG_X voltage is below the low limit, bits VDHI and VDLO will both be set to "0".
DESIGN NOTES
For all standard or cross-coupled squib IC configurations, the SQB_LO_XX terminal must be tied to a SENSE_XX terminal for either squib IC #1 or squib IC #2 (see Figure 7 and Figure 8). An active 600 A current sink is located in the SENSE_XX terminal. The sink current is used to pull the charge off the external EMC/filter caps after a diagnostic measurement has been made.
FIRING SUPPLY VOLTAGE (VFIRE_XX) DIAGNOSTICS ($C5 COMMAND)
This function monitors the voltage on the VFIRE_XX terminal. The supply voltage is compared to two thresholds (nominal and minimum) and will provide two bits of data to indicate if the terminal voltage is above, below, or in between the predetermined threshold levels. There is one diagnostic circuit for each VFIRE_XX terminal.
SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTICS ($C1 COMMAND)
This function monitors the voltage on the SENSE_XX terminals. The voltage is compared to two thresholds (minimum and maximum) and will provide two bits of data to indicate if the terminal voltage is above, below, or in between the predetermined threshold levels. When enabled, a 2.7 mA current source located in the SQB_HI_XX terminal is activated, sourcing current from the SQB_HI_XX to the SENSE_XX terminal. When resistive measurement legs to comparators located in the SENSE_XX terminal are activated, a fault on either side of the squib can be easily detected. An external current path that causes the SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal to be pulled below the minimum threshold, will be indicated as a "Short to Ground". If the SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal has an external current path that causes the terminal to be
VFIRE_XX SUPPLY VOLTAGE DIAGNOSTIC DATA RESULTS
If the VFIRE_XX voltage is above the high limit, bits VFHI and VFLO will both be set to "1". If the VFIRE_XX voltage is between the high limit and the low limit, bit VFHI will be set to "0" and VFLO will be set to "1". If the VFIRE_XX voltage is below the low limit, bits VFHI and VFLO will both be set to "0".
FIRING SUPPLY VOLTAGE DIAGNOSTICS, VDIAG_X V1, V2, V3, V4 ($C6 COMMAND)
The VDIAG_X V1, V2, V3, V4 function monitors voltage on the VDIAG terminals. The voltage being measured is then compared to four thresholds and will provide four bits of data to indicate if the terminal voltage is above, below, or between
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pulled above the maximum threshold, a "Short to Battery" will be indicated.
is shorted to Ground, the bit OPEN NO_SH_GND will be set to "0". During standard operation, both OPEN NO_SH_BATT and OPEN NO_SH_GND will be set to "1". Notes 1. This diagnostic circuit uses an internal 2.7 mA current source connected to the SQB_HI_XX terminal as a bias. If the SQB_LO_XX and SQB_HI_XX terminals have any capacitance (due to discrete capacitors or parasitic loading) the diagnostic condition will require a settling time based on the RC time constant. 2. With an OPEN NO_SH_GND or OPEN_NO_SH_BATT indicated, the SQB_HI_XX or SQB_LO_XX line contains the fault condition. The standard squib shortto-battery/ground diagnostics ($C1) can be executed to determine if the fault condition is on the SQB_HI_XX terminal or the SQB_LO_XX terminal.
SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTIC DATA RESULTS
If SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal is shorted to battery, the bit NO_SH_BATT will be set to "0". If a SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal is shorted to ground, the bit NO_SH_GND will be set to "0". During standard operation, both NO_SH_BATT and NO_SH_GND will be set to "1". Note This diagnostic circuit uses an internal 2.7 mA current source connected to the SQB_HI_XX terminal as a bias. If the SQB_LO_XX and SQB_HI_XX terminals have any capacitance (due to discrete capacitors or parasitic loading), the diagnostic condition will require a settling time based on the RC time constant.
SQUIB HARNESS SHORT-TO-BATTERY/GROUND DIAGNOSTICS WITH AN OPEN SQUIB ($C3 COMMAND)
This diagnostic function is to be used with no squib present (open squib condition) in the wiring harness. For an open squib condition, the function must monitor the voltage on the SQB_HI_XX and SQB_LO_XX terminals for "Short to Ground" and "Short to Battery" conditions. This function monitors the voltage on the SENSE_XX terminals. The voltage is compared to two thresholds (minimum and maximum) and will provide two bits of data to indicate if the terminal voltage is above, below, or in between the predetermined threshold levels. When enabled, a pair of opposing N-channel CMOS transistors are activated, creating roughly a 500 resistance between the SQB_HI_XX and SQB_LO_XX terminals together. A 2.7 mA current source located in the SQB_HI_XX terminal is activated, sourcing current from the SQB_HI_XX to the SQB_LO_XX terminal to the SENSE_XX terminal. When resistive measurement legs to comparators located in the SENSE_XX terminal are activated, a short to BAT/GND fault can easily be detected. An external current path that causes the SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal to be pulled below the minimum threshold, will be indicated as a "Short-to-Ground". If the SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal has an external current path that causes the terminal to be pulled above the maximum threshold, a "Short-to-Battery" will be indicated.
CONTINUITY TEST for the LOW-SIDE DRIVER SQB_LO_XX CONNECTION ($C2 COMMAND) (LOW-SIDE DRIVER CONTINUITY STATUS)
Low-side driver continuity is checked during the continuity test diagnostics. This function is used to check continuity at the SQB_LO_XX terminal connection. When enabled, a 2.0 mA current source located in the SQB_HI_XX terminal is activated sourcing current from the SQB_HI_XX to the SQB_LO_XX terminal. For a standard connection, the SQUIB_LO_XX_CON bit will be set to "1". With an open circuit connection, the SQUIB_LO_XX bit will be set to "0". The driver continuity information will be cleared after the information is transmitted on the next valid SPI command.
SQUIB RESISTANCE DIAGNOSTICS ($D0-$D3 COMMAND)
This function monitors squib resistance. When enabled, a diagnostic current derived from R_DIAG is passed through the selected squib. The resulting voltage across the squib is amplified and passed to an 8-bit voltage level detector. The eight bits of data will indicate if the selected squib has a resistance value above or below predetermined thresholds. The value of R_DIAG can be varied to allow the detection range to be altered. Increasing the value of R_DIAG will reduce the diagnostic current; thus, a higher squib resistance will be needed to reach the same RTH points. In the case that R_DIAG is a short-to-ground, the diagnostic current through the squib resistance will typically be less than 50 mA.
SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTIC DATA RESULTS
If SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal is shorted to battery, the bit OPEN NO_SH_BATT will be set to "0". If a SQB_LO_XX, SQB_HI_XX, or SENSE_XX terminal
SQUIB RESISTANCE DIAGNOSTIC DATA RESULTS
A comparator result bit set to "1" indicates that the input voltage is above the threshold resistance for that bit. Thus an open squib would cause all bits to be set to "1"; likewise, a shorted squib will cause all bits to be set to "0". Squib resistance tests are disabled during firing.
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FUNCTIONAL DESCRIPTION PROTECTION AND DIAGNOSIS FEATURES
SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB LINES (FIRING LOOPS) ($EX COMMAND)
This function monitors conditions that have shorts between squib lines (firing loops). When enabled, a 2.7 mA current source located in the SQB_HI_XX terminal is activated sourcing current from the selected SQB_HI_XX to the SENSE_XX terminal. The resulting voltage is checked on all other squib lines to determine if the squib lines are shorted. In applications using more than one squib driver IC, a separate command can also be issued to check all squibs for shorted squib lines.
SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB LINES DIAGNOSTIC DATA RESULTS (SHORTS BETWEEN FIRING LOOPS)
A comparator result bit set to "1" for SQUIB_XX indicates standard test current detected in squib line under test. A comparator result bit set to "0" for SQUIB_XX indicates faulty diagnostic current detected in squib line under test. A comparator result bit set to "1" for SQUIB_XX_SSQB_ YY indicates that the squib line is shorted to the squib under test. A comparator result bit set to "0" for SQUIB_XX_SSQB_YY indicates no shorted squib line detected (standard conditions). If more than two squibs are shorted together, the response will consist of all "0"s.
When FEN_1 or FEN_2 input is active high, the FEN_1 or FEN_2 function will be active high. When the FEN_1 or FEN_2 input state transitions from high to low, a programmable latching function will hold the FEN function active until the timeout of the FEN timer. The programmable latch and hold function will be capable of delays from 1.0 ms to 255 ms, in 1.0 ms increments. The timer is reset to programmed time when FEN_1 or FEN_2 terminal transitions from "0" to "1". The programmable counter delay will be set through an SPI command during module power-up/proveout. The default for the counter will be 0 ms. The bits FEN 1 and FEN 2 STATUS are a reflection of their respective terminals. The counter will be reset to 0-Sec time during a reset condition. Notes 1. Status information will be required to read counterprogrammed value. 2. Precautions need to be taken in the design to prevent the latching function from becoming a glitch catching function.
FEN 1 and FEN 2 COUNTER PROGRAMMING ($80 and $81 COMMAND)
The FEN 1 and FEN 2 counters require two separate 8-bit writes be made to the shift register. The first write is to unlock ($80 or $81) and reset the FEN counter registers in preparation of receiving a command. The second byte contains the programming information to set the required counter delay time (0 ms to 255 ms with 1.0 ms interval). Squib IC Power-Up default and $80 or $81 followed by $00 command will set the counter to 0 ms timer delay (refer to Table 8, page 23.) The FEN 1 and FEN 2 Counter programming status bits are a reflection of the counters programming. The programming status information can be compared to the data sent to ensure the squib driver was programmed properly. Counter programming status will be shifted from the shift register during the next read/write operation (Table 8). All unlock commands will be echoed back on the SPI Data output.
RESET (RST)
The Reset terminal has an internal current pull-down of typically 40 A. While this terminal is low, the internal functions of the squib driver IC are disabled and all data in the serial interface shift registers is cleared. This includes all FEN 1 and 2 counter programming, squib driver activation, and squib driver FET tests. With a minimum system VDD 4.1 V, the system reset bar threshold will be set to "0".
FEN_1 and FEN_2 (FEN) ($C8 COMMAND)
FEN_1 and FEN_2 have an internal current pull-down of typically 40 A. While the FEN terminal is low, firing of the FET drivers is disabled. All internal diagnostic functions and results will be available through the serial interface. The FEN terminal must be pulled high to enable firing of the FET drivers. Also, the terminal state can be used to turn the FET driver "ON" and "OFF" after the arm and fire command has been issued. (That is, once the FET drivers are turned on, pulling FEN_1 or FEN_2 low can turn the drivers off if the latch and hold function is not active, and pulling FEN_1 or FEN_2 high will activate the drivers if the fire command is still active). Status of FEN 1 and FEN 2 is contained in the C8 diagnostic byte, as shown in Table 7, Diagnostic Bit Definitions, page 22.) The FEN_1 and FEN_2 function should be capable of latching and holding the enable function for electronic safing function input. This function is required for dual-stage air bag applications. FEN_1 or FEN_2 will be considered active when either terminal is active ("1") for more than 12 ms. Tolerance range for the filter to be used will be 12 to 16 s.
FET DRIVER CURRENT LIMIT
A single resistor is used to set the current limit protection of the high-side drivers of both squib channels. The low-side current limit is never less than the high-side current limit. Table 9. RR_LIMIT_X Current Limit
RR_LIMIT_X 4.32 k 10 k 45.3 k VVFIRE = 7.0 V 0.92 A 1.37 A 2.0 A VVFIRE = 35 V 0.92 A 1.37 A 2.0 A
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Example of current limit conditions: RR_LIMIT_X =10 k, IHS = A A The high-side driver controls the current through the squib. The current limit for the low-side driver is only to protect the low-side driver stage from excessive current in the event of a short to battery. With RR_LIMIT_X conditions <4.32 k or shorted to ground, the current limit will default to the RR_LIMIT_X = 10 k current limit, not to exceed. With RR_LIMIT_X resistance value >60 k or open, the current limit will default to the RR_LIMIT_X = 10 k maximum current limit.
FET DRIVER CURRENT LIMIT MEASUREMENT ($7X COMMAND)
This function measures the firing current in each squib line and records the "ON" time in which the IMEAS is above the threshold for each squib. (Refer to Dynamic Electrical Characteristics table, page 12.) The timing registers can be reset via SPI command so additional current measurements can be made. An 8-bit message will be used to determine 255 time steps. The driver current limit measurement is activated when each individual high-side driver is activated. Each time the squib current is measured above the IMEAS threshold during the timer activation, a status bit will be set to "1". If the current measured is not above the IMEAS threshold during the timer activation, the timing data log bit will not increment. Each squib timing register can be reset via SPI command so additional current measurements can be made. Initial squib IC power-up will reset the timing registers (i.e., "Power-ON Reset"). When reset, the current limit measurement register byte will be set to $00. Command $79 will indicate the status of the current limit measurement comparator. The current limit measurement from the test is captured and loaded into the register on the next valid SPI command. When the firing current is above IMEAS, the current limit is activated and the status bit will be set to "1". If the firing current is below IMEAS, the current limit status bit will be set to "0".
With a shorted squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.090 ms. For the shorted squib load, the associated FET squib driver may enter thermal shutdown with an "ON" time of 2.09 ms tON 2.82 ms. When the thermal shutdown limit is exceeded, the thermal status will be set to "1". The thermal shutdown status ($7F) diagnostics latch the thermal bit status when executed. The Squib Driver Thermal shutdown status latch will be cleared after the information is transmitted on the next valid SPI command (i.e., TX: NOP or next $7F, latch cleared on rising edge of chip select). The FET squib driver can be activated through the arm/fire command when the TEMPRENABLE (MIN) is reached (thermal shutdown status "0").
VTRANTSTX, HIGH- AND LOW-SIDE SQUIB DRIVER FET TEST and STATUS ($82 TO $83 COMMAND)
This function checks the squib driver FET transistor status. The high- and low-side squib driver FET test requires FEN_1 and FEN_2 terminals to be low and two separate 8bit write commands to be made to the shift register. With the FEN_1 and FEN_2 terminals status LOW, the first write is to unlock in preparation of receiving the diagnostic command for testing the high- and low-side squib drivers. The unlock command ($82 and $83) is an "AND" function with the FEN_1 and FEN_2 BAR. All transistor test unlock commands ($82 and $83) will be echoed back on the SPI Data output. The high- or low-side squib driver FET test will be aborted if firing from any FET is enabled. During the first write (unlock command), all diagnostic functions are cleared. After the second write is completed, all other diagnostic functions are made available again. Squib 1A, squib 1B, squib 2A, and squib 2B high-side squib drivers will be activated and diagnosed by the $82 followed by $1X diagnostic command (refer to Table 8, page 24). A load from the SQB_HI_XX terminal to the SENSE_XX terminal is required for the high-side squib driver to be tested. Squib 1A, squib 1B, squib 2A, and squib 2B low-side squib drivers will be activated and diagnosed by the $83 followed by $2X diagnostic command (Table 8). When enabled the high- or low-side FET driver will be enabled and current limited to a nominal current limit of 10 mA. The high- and low-side driver test time is not automated and is controlled through SPI. When either a $82 or a $83 command is issued, the previous transistor test will stop to prevent coinciding highand low-side FET drive transistors from turning "ON". This prevents high- and low-side drivers from being activated simultaneously. Note The high- or low-side squib driver test is capable of checking a code sequence, allowing any combination of highor low-side drivers to be tested.
FET DRIVER CURRENT LIMIT MEASUREMENT RESET COMMAND ($3X COMMAND)
The current limit status registers can be individually reset with the command set found in Table 8. When the register bit is set to "1" for squib X, the current measurement register will be reset to $00.
SQUIB DRIVER THERMAL SHUTDOWN ($7F COMMAND)
With a nominal squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.09 ms. The individual squib driver thermal shutdown will not affect other squib drivers firing "ON" times.
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FUNCTIONAL DESCRIPTION PROTECTION AND DIAGNOSIS FEATURES
The diagnostic squib driver bit (HSDSTAT_X or LSDSTAT_X) will be set to "1" if the squib driver did not activate (turn "ON") during the diagnostic test. The diagnostic squib driver bit (HSDSTAT_X or LSDSTAT_X) will be set to "0" if the squib driver did activate (turn "ON") during the diagnostic test. Diagnostic data will be shifted from the shift register during the next read/write operation.
The diagnostic squib driver register will be set/cleared to "0" when the unlock command is loaded ($82 or $83 loaded with rising edge of CS). A diagnostic bit set to "0" indicates standard squib driver transistor operation.
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below.
10.3 7.6 7.4 C 5
1 32
B 9
2.65 2.35
30X
0.65
PIN 1 ID 4 B 9 11.1 10.9 C L
16
17
5.15
2X 16 TIPS
A
32X
SEATING PLANE
0.3 A B C A (0.29) 0.25 0.19 6 0.13
M BASE METAL
0.10 A
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
(0.203) 0.38 0.22 CA
M
A
R0.08 MIN 0.25
GAUGE PLANE
PLATING
MIN
0
0.29 0.13
B
8 8 0
ROTATED 90 CLOCKWISE
SECTION A-A
0.9 0.5 SECTION B-B
EK SUFFIX (32-LEAD SOIC) PLASTIC PACKAGE 98ARH99137A
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MC33797 Rev 2.0 07/2005

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